Title :
VLSI design and analysis of low power 6T SRAM cell using cadence tool
Author :
Khare, Kavita ; Khare, Nilay ; Kulhade, Vijendra Kumar ; Deshpande, Pallavi
Author_Institution :
Dept. of ECE, Maulana Azad Nat. Inst. of Technol., Bhopal
Abstract :
CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; integrated circuit design; low-power electronics; 6T SRAM cell; CMOS SRAM cell; VLSI design; bit-line voltage swings; cadence tool; low power; voltage 1.8 V; Batteries; CMOS technology; Circuit stability; Computer science; Differential amplifiers; Energy consumption; Random access memory; Read-write memory; Very large scale integration; Voltage; 6 Transistor SRAM Cell; Cell ratio; pull up ratio;
Conference_Titel :
Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Conference_Location :
Johor Bahru
Print_ISBN :
978-1-4244-3873-0
Electronic_ISBN :
978-1-4244-2561-7
DOI :
10.1109/SMELEC.2008.4770289