Title :
Design and implementation of a Viterbi decoder using FPGAs
Author :
Pandita, Bupesh ; Roy, Subir K.
Author_Institution :
Analog Devices, Bangalore, India
Abstract :
This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed
Keywords :
Viterbi decoding; code division multiple access; field programmable gate arrays; high level synthesis; modems; software prototyping; CDMA modems; FPGAs; Viterbi decoder; clocking mechanism; decision memory reading techniques; high level synthesis; path memory; rapid prototyping; Clocks; Counting circuits; Decoding; Field programmable gate arrays; Hamming distance; Hardware design languages; Prototypes; Quantization; Synchronization; Viterbi algorithm;
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
Print_ISBN :
0-7695-0013-7
DOI :
10.1109/ICVD.1999.745223
