Circuit Profiling Mechanisms for High-Level ATPG

Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we need to enable MVP´s ATPG to learn important details of the circuit under validation as a means to explore critical new circuit scenarios. In this paper, we present new profiling mechanisms that can exist either as a pre-processor that gathers circuit information prior to the circuit validation process, or as run-time entities that allow MVP to learn from its progressive experience.