• DocumentCode
    2554106
  • Title

    Functional Test Selection for High Volume Manufacturing

  • Author

    Gangaram, Vijay ; Bhan, Deepa ; Caldwell, James K.

  • Author_Institution
    Intel Corp., Folsom
  • fYear
    2006
  • fDate
    4-5 Dec. 2006
  • Firstpage
    15
  • Lastpage
    19
  • Abstract
    Validation and legacy test suites are often reused for achieving at speed coverage required for testing high frequency semiconductor chips. Porting validation tests to high volume manufacturing (HVM) flows involves extensive manual effort but is required to ensure high quality chips. Functional test selection is the problem of choosing a subset of tests from a large pool of existing tests to maximize the fault coverage while minimizing the test data volume, fault grading time and porting effort. We formulate a framework for test selection that allows various coverage metrics to be used for evaluation. A novel dynamic untestability analysis method is proposed to identify faults that can not be detected by a given test sequence. Conversely this method can be used to compute tight upper bound coverage and hence as a metric for functional test evaluation. Test selection using this new metric gives significant additional fault coverage than toggle based test selection.
  • Keywords
    fault diagnosis; integrated circuit design; semiconductor device manufacture; semiconductor device testing; dynamic untestability analysis method; fault coverage metric; functional test selection; high frequency semiconductor chip testing; high volume manufacturing; legacy test suite; toggle based test selection; validation test suite; Automatic testing; Computational modeling; Fault detection; Fault diagnosis; Frequency; Manufacturing; Microprocessors; Semiconductor device manufacture; Semiconductor device testing; Vehicle dynamics; Design Validation; Fault Simulation Acceleration; Functional Test Sequences; Test Sequence Compaction; Untestable Fault Identification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microprocessor Test and Verification, 2006. MTV '06. Seventh International Workshop on
  • Conference_Location
    Austin, TX
  • ISSN
    1550-4093
  • Print_ISBN
    0-7695-2839-2
  • Type

    conf

  • DOI
    10.1109/MTV.2006.12
  • Filename
    4197217