Dynamic threshold source coupled logic with pushpull topology for ultra low power applications

Subthreshold source coupled logic circuits (STSCL) are normally used for designing ultra-low power components and systems operating in the weak inversion (subthreshold) regime. This paper presents an implementation of a robust source coupled technique i.e. Dynamic threshold source coupled logic (DTSCL) with push pull amplifier at the output stage. The proposed circuit was analyzed to obtain minimum delay and power dissipation by varying the tail bias current. This circuit offered a very low power delay product (PDP) and was less sensitive to temperature and power supply variations. A tail bias current of the order of Pico amperes was capable of driving the circuit when implemented on 180nm CMOS technology. Measured results indicate that the simulated circuit offers a better performance for ultra-low power SCL circuits. Cadence virtuoso and Spectre simulation tools were used for simulating the circuit.