A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

Author

Cui, Zhiqiang ; Wang, Zhongfeng

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents a low-complexity, high-speed VLSI decoder architecture and its FPGA implementation for Euclidian geometry (EG) based quasi-cyclic (QC) low-density parity-check (LDPC) codes. In the design, various optimizations are employed to increase the clock speed. More parallelism is enabled for the partially parallel decoding architecture through the introduction of small hardware overhead. An efficient non-uniform quantization scheme is proposed to reduce the size of soft message memories without sacrificing the decoding performance. Synthesis results show that the proposed decoder for a (8176, 7156) EG-LDPC code can achieve a maximum (information) decoding throughput over 170 Mbps on Xilinx Virtex II FPGA when performing 15 iterations

Keywords

VLSI; field programmable gate arrays; high-speed integrated circuits; iterative decoding; parity check codes; quantisation (signal); 170 Mbit/s; EG-LDPC codes; Euclidian geometry; Xilinx Virtex II FPGA; field programmable gate array; low-complexity high-speed VLSI decoder architecture; nonuniform quantization scheme; partially parallel decoding architecture; quasicyclic LDPC decoder; quasicyclic low-density parity-check codes; soft message memories; Clocks; Design optimization; Field programmable gate arrays; Geometry; Hardware; Iterative decoding; Parity check codes; Quantization; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693778

Filename

1693778