DocumentCode :
2554517
Title :
A parallel LSI architecture for LDPC decoder improving message-passing schedule
Author :
Shimizu, Kazunori ; Ishikawa, Tatsuyuki ; Togawa, Nozomu ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution :
Graduate Sch. of Inf., Waseda Univ., Tokyo
fYear :
2006
fDate :
21-24 May 2006
Abstract :
This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) the column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently; and (ii) the proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead
Keywords :
decoding; integrated circuit design; large scale integration; parallel architectures; parity check codes; LDPC decoder; column operations; iterative decoding delay; message-passing schedule; parallel LSI architecture; pipelined architecture; row operations; Computer architecture; Delay; Hardware; Iterative algorithms; Iterative decoding; Large scale integration; Parity check codes; Processor scheduling; Production systems; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1693779
Filename :
1693779
Link To Document :
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