DocumentCode
2554623
Title
Time and cost reduction for 45° notch oriented 〈100〉 silicon substrate sample prepation
Author
bin Ahmataku, Handie ; Hock, Ling Chuan
Author_Institution
X-FAB Sarawak Sdn. Bhd., Kuching
fYear
2008
fDate
25-27 Nov. 2008
Firstpage
375
Lastpage
377
Abstract
Common method for sample preparation on 45deg notch oriented <100> silicon substrate requires cleaving followed by polishing technique. To prevent surface damage during polishing, top layer capping using epoxy cover-glass is required. A faster technique named as dasiaSupermanpsila method involves only cleaving has been proposed.
Keywords
elemental semiconductors; polishing; semiconductor growth; silicon; <100> silicon substrate; Si; cleaving; cost reduction; epoxy cover-glass; polishing; sample preparation; superman method; time reduction; top layer capping; Costs; Degradation; Etching; Finishing; MOSFETs; Protection; Silicon; Slurries; Springs;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Conference_Location
Johor Bahru
Print_ISBN
978-1-4244-3873-0
Electronic_ISBN
978-1-4244-2561-7
Type
conf
DOI
10.1109/SMELEC.2008.4770344
Filename
4770344
Link To Document