Circuit sizing method under delay constraint

In the last step of the design flow, circuit performance optimization is a difficult task to realize. The goal of this work is to avoid the use of CPU time expensive random mathematical methods, by defining an accurate and deterministic circuit sizing protocol, allowing easy and fast sizing of circuits at the required speed. We propose a coefficient based approach to solve the divergence branch problem for circuit sizing. Validation is given by comparing, in a standard 180nm CMOS process, the performance of different ISCAS benchmarks sized with an industrial tool and following our methodology