Efficient output transition time modeling in CMOS gates with ramp/exponential inputs

Author

Alioto, Massimo ; Palumbo, Gaetano ; Poli, Massimo

Author_Institution

Siena Univ.

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper, the modeling of the output transition time in deep-submicron (DSM) CMOS gates is discussed. In particular, the analysis starts from a previously proposed analytical model valid only for ramp inputs (Maurine et al., 2002 and Auvergne et al., 2000). This model is then improved by introducing two semi-empirical coefficients which have to be tuned by means of two SPICE simulations. Since an exponential input is more and more frequent in current DSM CMOS technologies, the model is extended to this kind of input waveform. Results are validated with simulations on a 0.18-mum CMOS technology. The output transition time model is found to be in good agreement with SPICE simulations, with an average error of only 5%

Keywords

CMOS integrated circuits; SPICE; circuit simulation; integrated circuit modelling; 0.18 micron; CMOS technology; SPICE; deep-submicron CMOS gates; Analytical models; CMOS logic circuits; CMOS technology; Circuit simulation; Degradation; Logic gates; Propagation delay; SPICE; Semiconductor device modeling; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693786

Filename

1693786