Efficient parallel hardware architecture for Lifting-Based discrete wavelet transform

Efficient parallel hardware architecture for lifting-based discrete wavelet transform is proposed in order to further decrease the hardware complexity of DWT. This architecture improves the parallel hardware architecture for discrete wavelet transform, adopts 2times2 transposing link, and optimizes the scaling link by leading in 4 to 1 multiplexer. Experimental results show that the proposed architecture, under the tight critical path, can decrease the used resources of internal registers and memories, at the same time save the arithmetic resources and hardware saving, and finally lower the hardware complexity of the discrete wavelet transform effectively.