Experimental analysis of read related transistors’ gate width sizing effects on the 3T1D DRAM access time curve

Unlike SRAMs, the access time of 3T1D DRAMs increase as the feature size becomes smaller. To combat this slow down, it has been suggested that the sizes of read related transistors be increased, a technique that has never been thoroughly explored. This paper deals with the exploration of the effects of the said technique, focusing on its effectiveness as a function of the width increase and how it holds up as feature sizes get smaller. Our results show that applying such technique sometimes has unexpected and surprising effects, including deviating the access time curve from its expected shape, and worse, even slowing the memory cell down even further at certain times-of-read. We also discovered that the effectiveness of the technique actually becomes more and more limited as feature sizes get smaller. At a smaller feature size, it would no longer be sufficient by itself, and would have to be combined with another technique to speed up the memory cell.