Programming and development environments for configurable computing systems

Author

Kumar, S. ; Bhatt, D. ; Vestal, S. ; Wren, B. ; Shackleton, J. ; Shirley, H. ; Bhatt, R. ; Golusky, J. ; Vojta, M. ; Nanavati, C. ; Zumsteg, P. ; Symosek, P. ; Crago, S. ; Schott, B. ; Parker, R. ; Gardner, G.

Author_Institution

Honeywell Technol. Center, Minneapolis, MN, USA

Volume

5

fYear

2000

fDate

2000

Firstpage

487

Abstract

Heterogeneous configurable computing systems containing general-purpose processors, special-purpose processors, field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) present several programming and development challenges. The ADAPTERS effort is addressing these challenges by focusing on three technology areas: (1) a unified data flow programming environment, (2) hardware/software partitioning and mapping tool, along with a system level modeling tool, and (3) a dynamic reconfiguration run-time environment for FPGAs. To investigate automatic mapping techniques, a constant false alarm rate (CFAR) application has been implemented on a combined PC/WILDFORCE platform. The combined platform containing FPGAs provided a 20% improvement in the end-to-end latency compared to a software solution running on a PC. An image compression example has also been developed to explore mode-based dynamic FPGA reconfiguration. The dynamic reconfiguration technology being developed can be used to adapt the behavior of systems, such as satellites, to changing internal and external conditions

Keywords

application specific integrated circuits; data flow computing; development systems; field programmable gate arrays; programming environments; reconfigurable architectures; ADAPTERS; PC/WILDFORCE; application specific integrated circuit; automatic mapping; constant false alarm rate; data flow programming; development environment; dynamic reconfiguration technology; field programmable gate array; general-purpose processor; hardware/software partitioning; heterogeneous configurable computing system; image compression; latency; programming environment; satellite; special-purpose processor; system-level modeling; Application software; Application specific integrated circuits; Delay; Dynamic programming; Field programmable gate arrays; Hardware; Integrated circuit technology; Programming environments; Runtime environment; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference Proceedings, 2000 IEEE

Conference_Location

Big Sky, MT

ISSN

1095-323X

Print_ISBN

0-7803-5846-5

Type

conf

DOI

10.1109/AERO.2000.878524

Filename

878524