Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses t_si were simulated. The source region was found to merge at t_si < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation region shows different shape and broaden in smaller t_si. For several channel lengths L_g les 100 nm, in the reduction of pillar thickness, the subthreshold slope (SS) tends to decrease, which indicate an increase in gate-gate charge coupling. Other short channel effect parameters (I_off, I_Dsat) show better improvement for lower pillar thickness, thus offer better performance and control.