FPGA-based time-to-digital converter for time-of-flight PET detector

We have developed a FPGA-based time-to-digital converter (TDC) that can be used for a TOF-PET block detector based on silicon photomultiplier (SiPM) photodetectors. The tapped delay line (TDL) method implemented with a dedicated carry chain structure was used to measure short time intervals. The proposed TDC, implemented in a Spartan-6 FPGA, consists of a fine time measurement block, a coarse counter, a ring oscillator and a multiplexer. The ring oscillator generates a delay chain related frequency which is used to compensate process, voltage and temperature (PVT) effects in real-time without causing dead-time in the TDC. The multiplexer allows multiple channels to share the same delay chain which effectively reduces the amount of FPGA resources. As the TDC is implemented in an shared FPGA device, which already exists in a data acquisition system (DAQ), TOF capability can be implemented easily without requiring more resources. The performance of our proposed TDC was first measured with two input pulses which were generated from a pulse generator but with different delay lengths. Timing resolution of a TDC channel is 41.6 ± 1.1 ps FWHM (17.7 ± 0.5 ps RMS). The proposed TDC was also used to measure the timing resolution of a pair of TOF-PET detector with a Hamamatsu MPPC coupled to a 3 mm × 3 mm face of a 2 mm × 2 mm × 3 mm LYSO crystal. The measured coincidence time resolution was 197 ± 4 ps FWHM which agreed with the value measured by a high speed oscilloscope (195 ± 7 ps FWHM). These results verify the feasibility of our TDC for TOF-PET applications.