Digital background calibration of pipeline ADC with open-loop gain stage

Author

Tavassoli, B. ; Shoaei, O.

Author_Institution

Dept. of ECE, Tehran Univ.

fYear

2006

fDate

21-24 May 2006

Lastpage

5258

Abstract

In this work, a digital background calibration method for pipelined ADC is proposed which can compensate for the nonlinearity in amplifier gain. The proposed scheme is based on input statistical distribution property which is assumed to be known. The error correction is completely performed in digital domain. In analog domain it is only necessary to add two comparators for generating calibration threshold. Results show an improvement of 16 dB in SNDR for a nonlinear gain stage designed in a 1.5 V supply and 0.35 mum CMOS technology

Keywords

CMOS integrated circuits; analogue circuits; analogue-digital conversion; calibration; error compensation; error correction; operational amplifiers; pipeline processing; statistical distributions; 0.35 micron; 1.5 V; CMOS technology; analog domain; comparators; digital background calibration; digital domain; error correction; open-loop gain stage; pipeline ADC; statistical distribution property; Analog-digital conversion; CMOS technology; Calibration; Capacitors; Digital integrated circuits; Error correction; Pipelines; Sampling methods; Signal design; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693818

Filename

1693818