Energy efficient implementation of 16-Bit ALU using block enabled clock gating technique

The need to design and develop high performance and high speed VLSI systems such as NOCs in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. In such devices managing the power among the domains of a system is of real concern. Hence, the low power design techniques namely: clock gating, power gating, dynamic voltage scaling and frequency scaling are of most important. In this paper the clock gating technique is applied to a 16-bit ALU. In the this work the ALU is divided into two functional units namely: Arithmetic unit and Logical Unit. The demultiplexer is used as a selector of the functional unit for which the clock is applied. The design is simulated using QuestaSim power aware simulator, implemented and synthesized using Precision synthesis tool on a Spartan 6 FPGA. Power analysis is carried out using Xilinx XPower analyzer. The design is tested for a wide band of frequencies from 1MHz to 5000MHz. The Clock and dynamic power reduction is observed for lower frequencies but for high frequency the target device has the limitation. The clock gating technique when applied to the design it is observed that the clock power is reduced by an average of 70% for lower frequencies and an average of 30% for higher frequencies. This reduction is at the cost increase in area by 2%.