• DocumentCode
    2555837
  • Title

    Low power and power aware fractional motion estimation of H.264/AVC for mobile applications

  • Author

    Chen, Tung-Chien ; Chen, Yu-Han ; Tsai, Chuan-Yung ; Chen, Liang-Gee

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    In this paper, the low power design techniques from algorithm to architecture levels are proposed for fractional motion estimation in H.264/AVC. The proposed AMPD algorithm can reduce 50.8% power with up to 0.1 dB quality drop. The proposed parallel architecture with efficient memory hierarchy can efficiently reuse data and save 61.6% power. Furthermore, the power aware functionality is included. Our design can gracefully vary the quality degradation of 0.1-3.9 dB in response to the 22.58-1.64 mW power consumption. This power-oriented design is very efficient for different mobile applications in various power situations
  • Keywords
    logic design; low-power electronics; motion estimation; video coding; 1.64 to 22.58 mW; H.264/AVC; fractional motion estimation; logic design; mobile applications; power-oriented design; video coding; Automatic voltage control; Circuits; Computer architecture; Digital signal processing; Energy consumption; Hardware; Interpolation; Motion estimation; PSNR; Parallel architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693837
  • Filename
    1693837