Title :
A 1-V 12-bit switched-op amp pipelined ADC with power optimization
Author :
Nabavi, Mohammad R.
Author_Institution :
Dept. of Electr. Eng., Mashhad Ferdowsi Univ.
Abstract :
In this paper, a very low-voltage low-power high-resolution pipelined ADC is presented. Several challenges in very low voltage high resolution ADC design are addressed and a low-power design methodology for swithched-opamp (SO) converters is presented. This methodology determines the optimum values of all capacitors, including the compensation capacitors of the opamps and also the stage resolutions that will lead to minimum power consumption for a specified value of signal-to-noise ratio. A novel 2.5-bit stage is also presented. Design considerations and simulation results of the 12-bit 1-V 10-MS/s pipelined SO ADC with low power consumption are addressed. The effective number of bits is 11.2 for a 1-MHz 1.2Vp-p,diff input signal
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; operational amplifiers; 1 MHz; 1 V; 1.2 V; 2.5 bit; analog-to-digital converter; compensation capacitors; operational amplifiers; pipelined ADC; swithched-opamp converters; Capacitors; Circuit noise; Clocks; Energy consumption; Feedback; Power dissipation; Signal design; Signal resolution; Signal to noise ratio; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693844
