Title :
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique
Author :
Lin, Jin-Fu ; Chang, Soon-Jyh
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Abstract :
In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the high-linearity requirement of the op-amp, a new type of SHA circuit is presented
Keywords :
analogue-digital conversion; sample and hold circuits; finite gain; modified time-shifted correlated double sampling; operational amplifier; pipelined analog-to-digital converter; sample and hold circuit; Analog-digital conversion; Circuits; Error correction; Gain; Linearity; Operational amplifiers; Power dissipation; Power supplies; Sampling methods; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693846
