Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells

This paper proposes a minimum-width multi-row transistor placement method for CMOS cells in presence of non-dual P and N type transistors. This is the first exact multi-row transistor placement method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. Moreover, the proposed method uses more efficient gate connection style, and generates more area-efficient transistor placements than the conventional method. Experimental results show that the proposed method can generate the minimum width multi-row transistor placement of the cells with up to 26 transistors in reasonable time