Title :
A congestion-driven buffer planner with space reservation
Author :
Huang, Hsin-Hsiung ; Chen, Yung-Ching ; Hsieh, Tsai-Ming
Author_Institution :
Inst. of Electron. Eng., Chung Yuan Christian Univ., Chung-Li
Abstract :
In this paper, we present a new algorithm of the four-stage buffer planning to improve success rates of buffer insertion and wiring congestion. It is based on the space reservation, which reserves enough dead space between all adjacent blocks. First of all, we perform the space reservation between all adjacent blocks of an initial floorplan. Second, the shortest path graph is used to select the routing path for each net. Third, the algorithm finds all buffer locations which meet the timing constraints for all nets. Finally, compact the layout to delete the redundant area. Compared to the traditional method, such as channel insertion, our algorithm can reserve enough silicon space for buffer insertion without moving blocks which lead to a large re-computation and area expansion. Experimental results clearly show the superiority of our method to the traditional method without space reservation
Keywords :
graph theory; integrated circuit interconnections; integrated circuit layout; network routing; buffer insertion; buffer locations; channel insertion; congestion-driven buffer planner; four-stage buffer planning; initial floorplan; routing path; shortest path graph; space reservation; wiring congestion; Crosstalk; Delay; Planing; Polynomials; Routing; Silicon; Space technology; Timing; Wire; Wiring;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693863