Real-time Stereo Vision FPGA Chip with Low Error Rate

As a step towards real-time stereo, we will present a fast and efficient VLSI architecture and implementation of a stereo matching algorithm which has a low error rate. The architecture has the form of linear systolic array using simple processing element (PE)s that are connected with neighboring PEs. Due to this simple full parallel structure, it is smaller in the time complexity load than other methods. Thus our structure is more adequate for high resolution and real-time applications like the 3D video conference, the Z- keying,and the virtual reality. Our chip can process 320 by 240 images of 128 levels at 30 frames/s.