Stabilized Linear Operation of CMOS Power Transistors for Si-RF Transceiver Integration

We report on stabilization of CMOS power transistors employing a new layout concept. We assume that instability of power transistors is caused by intensified impact ionization at the pinch-off channels, and that the impact ionization is synchronized with acoustic standing waves in the device area if they are designed with conventional layout configurations. In the new layout design, gate fingers are electrically connected in parallel, but thermally and geometrically isolated from one another at random intervals. The shape of the device area is deformed so that acoustic waves are scattered at the boundaries of device area surrounded by shallow trench isolation (STI). Measurements demonstrated that the stability of transistors has been improved. For example, a transistor with a gate width of 800 mum has shown the 1 dB-compression point P_1dB of 15 dB_m and the saturation power P_SAT of 21 dB_m at 2.45 GHz under a bias condition for linear operation. The results indicate that the CMOS transistors are suitable for power amplifiers, especially, for full integration of wireless transceivers.