Title :
Variation study of process parameters in Trigate SOI-FinFET
Author :
Singh, D. ; Mohapatra, S.K. ; Pradhan, K.P. ; Sahu, P.K.
Author_Institution :
Dept. of Electr. Eng., Nat. Inst. of Technol. (NIT), Rourkela, India
Abstract :
This work presents the simulation of quantum transport in tri-gate (TG) silicon-on-insulator (SOI) FinFET using 3-D numerical simulation. The impact of process parameters like fin height (HFin), fin width (WFin), length of underlap (Lun) in both source and drain side are investigated using Sentaurus device simulator. The effectiveness and optimization of the process parameters required in SOI FinFETs to enable them catch up with the DC performance are systematically investigated. The performances such as threshold voltage (Vth), on current (Ion), off current (Ioff), transconductance (gm) and transconductance generation factor (TGF=gm/ID) of FinFET are analyzed. The results show for HFin/Lg=0.8 and WFin/Lg=0.6 have higher Ion and lower Ioff which is more suitable for circuit applications.
Keywords :
MOSFET; numerical analysis; semiconductor device models; silicon-on-insulator; 3D numerical simulation; Sentaurus device simulator; Si; fin height; fin width; process parameters; quantum transport; silicon-on-insulator; threshold voltage; transconductance generation factor; trigate SOI-FinFET; underlap length; variation study; FinFETs; Leakage currents; Logic gates; Mathematical model; Performance evaluation; Semiconductor process modeling; Transconductance; Device geometry; Process parameters variability; SOI-FinFET; Tri-Gate;
Conference_Titel :
India Conference (INDICON), 2014 Annual IEEE
Conference_Location :
Pune
Print_ISBN :
978-1-4799-5362-2
DOI :
10.1109/INDICON.2014.7030601
