Variation study of process parameters in Trigate SOI-FinFET

Author

Singh, D. ; Mohapatra, S.K. ; Pradhan, K.P. ; Sahu, P.K.

Author_Institution

Dept. of Electr. Eng., Nat. Inst. of Technol. (NIT), Rourkela, India

fYear

2014

fDate

11-13 Dec. 2014

Firstpage

1

Lastpage

4

Abstract

This work presents the simulation of quantum transport in tri-gate (TG) silicon-on-insulator (SOI) FinFET using 3-D numerical simulation. The impact of process parameters like fin height (H_Fin), fin width (W_Fin), length of underlap (L_un) in both source and drain side are investigated using Sentaurus device simulator. The effectiveness and optimization of the process parameters required in SOI FinFETs to enable them catch up with the DC performance are systematically investigated. The performances such as threshold voltage (V_th), on current (I_on), off current (I_off), transconductance (g_m) and transconductance generation factor (TGF=g_m/I_D) of FinFET are analyzed. The results show for H_Fin/L_g=0.8 and W_Fin/L_g=0.6 have higher I_on and lower I_off which is more suitable for circuit applications.

Keywords

MOSFET; numerical analysis; semiconductor device models; silicon-on-insulator; 3D numerical simulation; Sentaurus device simulator; Si; fin height; fin width; process parameters; quantum transport; silicon-on-insulator; threshold voltage; transconductance generation factor; trigate SOI-FinFET; underlap length; variation study; FinFETs; Leakage currents; Logic gates; Mathematical model; Performance evaluation; Semiconductor process modeling; Transconductance; Device geometry; Process parameters variability; SOI-FinFET; Tri-Gate;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2014 Annual IEEE

Conference_Location

Pune

Print_ISBN

978-1-4799-5362-2

Type

conf

DOI

10.1109/INDICON.2014.7030601

Filename

7030601