5 GHz 11-Stage CML VCO with 40% Frequency Tuning in 0.13μm SOI CMOS

Author

Kim, Daeik D. ; Cho, Choongyeun ; Kim, Jonghae

Author_Institution

Semicond. R&D Center, IBM, Hopewell Junction, NY

fYear

2009

fDate

19-21 Jan. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents a manufacturable CML-based 11-stage VCO for digital system clock fabricated in 0.13 mum SOI CMOS. The 11-stage design enables quality oscillation, wide frequency tuning range, and process variability rejection. On average, the VCO exhibits 40% frequency tuning range from 4.23 to 6.35 GHz. The VCO phase noise is -129.8 dBc/Hz at 10 MHz offset in current-controlled measurements, and average FoMT(10%) is -178.1 dBc/Hz. Full 200 mm wafer scan result is presented along the phase noise measurement to demonstrate a statistical methodology.

Keywords

CMOS integrated circuits; MMIC oscillators; circuit tuning; clocks; current-mode logic; digital phase locked loops; field effect MMIC; phase noise; silicon-on-insulator; voltage-controlled oscillators; 11-stage CML VCO; 200 mm wafer scan; FoMT; SOI CMOS; current-controlled measurements; current-mode logic; digital PLL; digital system clock; frequency 4.23 GHz to 6.35 GHz; frequency tuning; phase noise measurement; size 0.13 micron; voltage controlled oscillator; Clocks; Current measurement; Digital systems; Frequency; Noise measurement; Phase measurement; Phase noise; Pulp manufacturing; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4244-3940-9

Electronic_ISBN

978-1-4244-2831-1

Type

conf

DOI

10.1109/SMIC.2009.4770501

Filename

4770501