FPGA-based architecture for real-time IP video and image compression

Three-dimensional imaging applications require high resolution images that finally result in high data volumes. Due to bandwidth and storage restrictions, an efficient and robust compression scheme must be developed in order to overcome these limitations. This work presents a hardware implementation of a real-time disparity estimation scheme targeted but not limited to integral photography (IP) 3D imaging applications. The proposed system demonstrates an efficient architecture which copes with the increased bandwidth demands that 3D imaging technology requires. Moreover, the system can successfully process high resolution IP video sequences in real-time