Topological and functional partitioning in EM analysis: Application to wafer-level chip-scale harmonic filters

Aggressively applied function and geometry oriented partitioning is proposed for design and analysis of RF harmonic filters. The efficiency of the proposed methodology is demonstrated by application to the RF portion of an NXP semiconductor transceiver design. Simulation is compared to measurement at both component and function-block levels. Limits of partitioning assumptions in comparison with full-electromagnetic model approaches are discussed. Guidelines and design rules for partitioning of scalable multi-port sub-structures for back analysis in circuit simulator frameworks are studied.