Title :
A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues
Author :
Ishii, Y. ; Fujiwara, H. ; Tanaka, S. ; Doguchi, T. ; Kuromiya, O. ; Chigasaki, H. ; Tsukamoto, Y. ; Nii, K. ; Kihara, Y. ; Yanagisawa, K.
Author_Institution :
Renesas Electron. Corp., Japan
Abstract :
We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (Vmin) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured screening of failures in the write/read disturb operations.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; nanoelectronics; 8T dual-port SRAM; asynchronous operation; circuit technique; dual-port SRAM macro; low-power CMOS technology; screening circuitry; size 28 nm; write-read disturb condition; write-read disturb failure issue; write-read disturb operations; Clocks; Delay; Logic gates; Monte Carlo methods; Random access memory; Semiconductor device measurement; Synchronization;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716538
