Title :
Source-drain engineering for Sub-90 nm junction-field-effect transistors
Author_Institution :
Silterra USA, Inc., San Jose, CA, USA
Abstract :
This paper presents sub-90 nm symmetric and asymmetric source-drain junction-field-effect transistor (JFET) devices for ultra-low voltage operation. The JFET devices are suitable for ultra-low voltage analog applications by overcoming the limitations of advanced MOSFET devices and CMOS technologies. However, the performance of sub-90 nm channel-JFETs is limited by higher off-state leakage current and lower ON/OFF current ratio. In this paper, we introduce asymmetric source-drain device architecture to improve the ON/OFF performance of JFET devices. The numerical device simulation results show that the proposed asymmetric devices significantly reduce the off-state leakage current in contrast to the symmetric devices for high performance operation at ultra-low power supply voltage of 0.5 V.
Keywords :
analogue integrated circuits; junction gate field effect transistors; leakage currents; low-power electronics; numerical analysis; JFET device; asymmetric source-drain device architecture; junction-field-effect transistor; lower ON/OFF current ratio; numerical device simulation; off-state leakage current; size 90 nm; source-drain engineering; ultra-low voltage analog application; ultra-low voltage operation; voltage 0.5 V; CMOS integrated circuits; CMOS technology; Circuit synthesis; Electron devices; Leakage current; MOSFET circuits; Medical simulation; Power supplies; Threshold voltage; Transistors; Low-power device; analog applications; asymmetric source-drain; channel-JFET; double-gate JFETs; ultra-low voltage device;
Conference_Titel :
Electron Devices and Semiconductor Technology, 2009. IEDST '09. 2nd International Workshop on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4244-3831-0
Electronic_ISBN :
978-1-4244-3832-7
DOI :
10.1109/EDST.2009.5166094
