DocumentCode
2559151
Title
Future device scaling - Beyond traditional CMOS
Author
Tyagi, S. ; Auth, C. ; Ban, I. ; Chang, P. ; Chau, R. ; Ghani, T. ; Jan, C.-H. ; Kavalieros, J. ; Kuhn, K. ; Maiz, J. ; Mistry, K. ; Post, I.
Author_Institution
Intel India Technol., Bangalore, India
fYear
2009
fDate
1-2 June 2009
Firstpage
1
Lastpage
4
Abstract
Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore´s law.
Keywords
CMOS integrated circuits; semiconductor technology; CMOS; Moore law; device scaling; CMOS process; CMOS technology; Material properties; Materials reliability; Moore´s Law;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Semiconductor Technology, 2009. IEDST '09. 2nd International Workshop on
Conference_Location
Mumbai
Print_ISBN
978-1-4244-3831-0
Electronic_ISBN
978-1-4244-3832-7
Type
conf
DOI
10.1109/EDST.2009.5166098
Filename
5166098
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