Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bias

This paper presents a compilable SRAM augmented with a sleep mode to achieve low standby power. Sleep transistor and source line self bias are added to the array, and their layouts fit to the repetitive cell placement. The area overhead is minimized in such a way that the footprint remains the same. A 0.18 mum 512 Kb test chip manufactured by two different foundries is used to demonstrate its effectiveness. The standby current measurements show substantial savings of 69% and 77%, respectively, at 1.8 V. The savings can be greater if the supply voltage is lowered. This encourages sleeping at low voltage. Design choices to vary the virtual ground voltage to attain further reduction are investigated. The tradeoff is with the data retention voltage which is measured at least 0.1 V higher. The fact that the cell stability is undermined in the sleep mode is the main concern to operate the SRAM at low voltage.