Title :
OPTIMOS: A branch-level digital circuit optimizer
Author :
Zaker, S. ; Zahnd, J.
Author_Institution :
Lab. de Syst. Logiques, Ecole Polytech. Federale de Lausanne, Switzerland
Abstract :
The authors describe branch-level circuit optimization as an approach to optimization based transistor sizing for digital MOS VLSI circuits. It is shown that this approach compares favorably to previous optimization work at gate level. Branch-level optimization is finer-grained and produces circuits that are both smaller and faster. A fast optimization algorithm suitable for interactive design is also proposed. OPTIMOS, a CAD tool implementing these concepts in a complexity interactive optimization environment is also presented
Keywords :
CMOS logic circuits; VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; CAD tool; CMOS gate; OPTIMOS; branch-level digital circuit optimizer; complexity interactive optimization environment; digital MOS VLSI circuits; fast optimization algorithm; interactive design; optimization based transistor sizing; Algorithm design and analysis; Circuit optimization; Constraint optimization; Delay estimation; Design automation; Design optimization; Digital circuits; MOSFETs; Silicon; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386415
