A 12-bit 800-MS/s switched-capacitor DAC with open-loop output driver and digital predistortion

A 12-bit 800-MS/s DAC implemented in 90-nm CMOS is presented. The design uses three interleaved, pipelined, switched-capacitor cores followed by an open-loop output driver. The driver is linearized using digital predistortion. Measured SFDR is greater than 58 dB for signal frequencies below 200 MHz, and greater than 53 dB for signal frequencies below 400 MHz, all with output swings as large as 2.9 V, peak-to-peak differential. Power dissipation is 103 mW when delivering a full-scale signal current of 16 mA.