Title :
A 10b 320MS/s self-calibrated pipeline ADC
Author :
Hung-Wei Chen ; Shen, Wei-Ting ; Cheng, Wei-Chih ; Hsin-Shu Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A high-speed low-power self-calibrated pipeline ADC is presented. Gain error due to low-gain opamp used in multiplying DAC (MDAC) is corrected by the proposed foreground calibration technique. It adjusts the inter-stage gain by connecting a calibration capacitor into the MDAC positive feedback path. It only requires 168 clock cycles to complete the calibration without external precise references. The calibration circuit does not consume power during normal conversion. The prototype ADC in 90 nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 dB and 54.2dB. The total power dissipation is 42 mW and it occupies an active chip area of 0.21 mm2 Its figure-of-merit (FOM) is 442 fJ/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; capacitors; digital-analogue conversion; feedback; low-power electronics; operational amplifiers; MDAC positive feedback path; SNDR; calibration capacitor; calibration technique; clock cycle; gain 54.2 dB; gain 66.7 dB; interstage gain; low-gain opamp; low-power CMOS technology; peak SFDR; pipeline ADC; power 42 mW; power dissipation; size 90 nm; word length 10 bit; Bandwidth; Calibration; Capacitors; Clocks; Gain; Pipelines; Registers; Pipeline analog-to-digital converter (ADC); interstage gain; low-gain opamp; self-calibrated;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716583
