DocumentCode
2559647
Title
A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL
Author
Cho, Joo-Hwan ; Lee, Ki-Won ; Choi, Byoung-Jin ; Lee, Geun-Il ; Na, Kwang-Jin ; Jung, Ho-Don ; Lee, Woo-Young ; Park, Ki-Chon ; Joo, Yong-Suk ; Cha, Jae-Hoon ; Kim, Se-Jun ; Choi, Young-Jung ; Moran, Patrik B. ; Ahn, Jin-Hong ; Ki, Joong-Sik
Author_Institution
Hynix Semicond. Inc., Ichon
fYear
2006
fDate
13-15 Nov. 2006
Firstpage
39
Lastpage
42
Abstract
A 1.5V, 512 Mbit GDDR4 SDRAM using a 90-nm DRAM process has been developed. The data rate is 3.2 Gbps/pin, which corresponds to 12.8 GBps in x32 GDDR4 based I/O. A multi-divided architecture consisting of 4 independent 128 Mb core arrays is designed to reduce power and output noise. Also, a dual-clock system, 4 phase data input strobe scheme and 4 phase fully analog DLL are used to increase internal timing margins.
Keywords
DRAM chips; computer graphics; timing circuits; analog DLL; dual-clock system; graphic DDR4 SDRAM; internal timing margins; voltage 1.5 V; Circuit noise; Clocks; Frequency; Graphics; Jitter; Noise reduction; Random access memory; SDRAM; Semiconductor device noise; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location
Hangzhou
Print_ISBN
0-7803-9734-7
Electronic_ISBN
0-7803-97375-5
Type
conf
DOI
10.1109/ASSCC.2006.357846
Filename
4197585
Link To Document