Effective march algorithms for testing single-order addressed memories

The testing problems for the single-order addressed (SOA) memory, are discussed and a family of test algorithms for it are presented. SOA memories are used in various applications, such as FIFOs, where the sequence of addressing need to be in a certain order, more specifically in a single-order (e.g., from address 0 to n-1). Consequently this restricted addressing capability allows faster address generation, and hence shorter overall access time. The existing march test algorithms, which are developed to test random-access memories, cannot be adopted by the users of SOA memories, due to the fact that all these algorithms march through the memory in two directions; whereas SOA memories are limited in terms of address order to a single direction. However, the existing march tests provide a basis for a new family of algorithms targeting SOA memories. These algorithms can be used as externally applied tests or can be implemented as BIST hardware