Title :
2.07 GHz floating-point unit with resonant-clock precharge logic
Author :
Jerry, C.K. ; Ma, Wei-Hsiang ; Kim, Suhwan ; Papaefthymiou, Marios
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
This paper presents an 8-cycle 64 FO4 single-precision fused-multiply-add floating-point unit (FPU) chip with fine-grain resonant clocking and dynamic-evaluation static-latch logic to achieve dynamic-logic levels performance with significant power reduction. Fabricated in a 90nm low-power RVT technology, the resonant FPU achieves clock speeds up to 2.07GHz. At its resonant frequency of 1.81GHz, it dissipates 334mW, yielding 31.5% lower power and 32% more GFLOPS/W over a conventionally-clocked version of the same FPU implemented on the same die.
Keywords :
adders; clocks; flip-flops; floating point arithmetic; logic design; low-power electronics; multiplying circuits; GFLOPS/W; dynamic-evaluation static-latch logic; dynamic-logic levels performance; fine-grain resonant clocking; frequency 1.81 GHz; frequency 2.07 GHz; low-power RVT technology; power 334 mW; resonant-clock precharge logic; single-precision fused-multiply-add floating-point unit chip; size 90 nm; Capacitance; Clocks; Frequency measurement; Generators; Logic gates; Resonant frequency; Synchronization;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716593