Title :
GENRIF: An integrated VLSI FIR filter compiler
Author :
Bidet, E. ; Joanblanq, C. ; Senn, P.
Author_Institution :
France Telecom, CNET Grenoble, Meylan, France
Abstract :
An integrated VLSI FIR filter compiler tool targeted at sampling rates from 0 to more than 100 MHz is described. Main features are high-level synthesis and optimization of FIR filter coefficients with respect to frequency specifications, a priori and a posteriori verification of filter response (including finite word length effects), and layout generation based on a bit-parallel architecture. The tool is fully integrated within the GDT environment (Mentor Graphics)
Keywords :
FIR filters; VLSI; application specific integrated circuits; circuit layout CAD; circuit optimisation; frequency response; high level synthesis; 0 to 100 MHz; ASIC design; GDT environment; GENRIF; bit-parallel architecture; filter response; finite word length effects; frequency specifications; high-level synthesis; integrated VLSI FIR filter compiler; layout generation; optimization; Circuit synthesis; Digital signal processing; Finite impulse response filter; Gas discharge devices; IIR filters; Layout; Program processors; Signal processing algorithms; Telecommunications; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386431
