Title :
A skew assumption logic simulation technique for potential spike detection
Author :
Oguri, Sumio ; Okabe, Tetsuya ; Murai, Shinichi ; Hosomi, Shunsuke ; Uzaki, Hiroshi
Author_Institution :
Mitsubishi Electric Corp., Japan
Abstract :
A simulation technique that a set of signal transitions which may cause the simulated circuit to exhibit incorrect behavior by assuming event skew is described. Incorporation of timing check primitive enables detailed timing error messages composed of the past signal transitions at the primary inputs which cause the error, the internal gate which generates the potential spike signal and the internal signal transitions related to the error. The logic simulator on which the novel simulation technique is installed helps designers to find hazardous designs in the circuit under verification. LSIs verified by using the simulator are free from timing skew troubles on the bench of ATE (Automatic Test Equipment)
Keywords :
circuit analysis computing; logic CAD; logic gates; timing; LSIs; circuit under verification; hazardous designs; logic simulation technique; past signal transitions; potential spike detection; skew assumption; timing check primitive; timing error messages; timing verification; Accuracy; Analytical models; Application specific integrated circuits; Circuit simulation; Computational modeling; Design engineering; Discrete event simulation; Logic circuits; Propagation delay; Timing;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386432