A 300- to 800-MHz de-skew clock generator for arbitrary delay

A low-jitter 300- to 800-MHz de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while maintaining a wide loop bandwidth. The clock skew problem is detrimental in the high speed applications, especially when the skew is longer than multi-cycles. The proposed generator was fabricated in a 0.18-μm CMOS process. The clock generator achieves a measured RMS jitter of 5.8 ps at 800 MHz with less than 100-ns settling time. The total area is 0.525 × 0.396 mm² and the power consumption is 10.8 mW from a 1.8V supply.