• DocumentCode
    2560056
  • Title

    Parasitic discrete-time-pole cancelling techniques for ultra-wideband discrete-time charge-domain baseband filters

  • Author

    Yoshizawa, Atsushi ; Iida, Sachio

  • Author_Institution
    Sony Corp., Tokyo, Japan
  • fYear
    2010
  • fDate
    8-10 Nov. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Parasitic discrete-time-pole cancelling techniques that use a discrete-time IIR BPF are presented. Parasitic capacitors, which usually cause undesirable lowpass parasitic discrete-time poles in ultra-wideband applications, are utilized to provide bandpass parasitic discrete-time poles, thus improving the frequency characteristics in parallel with passband equalizer circuits. A novel charge transfer scheme that reduces the parasitic sensitivity of the output nodes is also implemented. The prototype filter has been implemented with a 90 nm CMOS technology. Measurements show that a 250-MHz cutoff, 0-db gain discrete-time charge-domain filter and an 8-phase clock pulse generator dissipate 8 mA and 1 mA, respectively, from a 1.2-V supply voltage.
  • Keywords
    CMOS integrated circuits; IIR filters; band-pass filters; capacitors; clocks; discrete time filters; equalisers; pulse generators; ultra wideband technology; CMOS technology; charge transfer; clock pulse generator; current 1 mA; current 8 mA; discrete-time IIR band-pass filters; frequency 250 MHz; parasitic capacitors; parasitic discrete-time-pole cancelling; passband equalizer circuits; size 90 nm; ultra-wideband discrete-time charge-domain baseband filters; voltage 1.2 V; Band pass filters; Capacitance; Capacitors; Clocks; Finite impulse response filter; IIR filters; Passband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-8300-6
  • Type

    conf

  • DOI
    10.1109/ASSCC.2010.5716605
  • Filename
    5716605