Power estimation for high level synthesis

Author

Landman, Paul E. ; Rabaey, Jan M.

Author_Institution

Electr. Eng. Dept., Univ. of California, Berkeley, CA, USA

fYear

1993

fDate

22-25 Feb 1993

Firstpage

361

Lastpage

366

Abstract

Techniques for rapidly and accurately estimating power consumption based on high level descriptions of system architectures are described. This approach, based on stochastic modeling of bus statistics, achieves the accuracy traditionally associated with gate and circuit level estimation tools while exploiting the reduced computational complexity offered by the architectural level of abstraction. The results presented indicate an estimation accuracy within 9.4% of gate level simulations, while existing high level techniques can be off 80% or more

Keywords

circuit analysis computing; high level synthesis; logic CAD; stochastic processes; CAD design space; RAM memory module; architectural level of abstraction; bus statistics; high level synthesis; power consumption; power estimation; reduced computational complexity; stochastic modeling; Circuit simulation; Computational modeling; Delay estimation; High level synthesis; Personal communication networks; Power system modeling; Radio access networks; Statistics; Stochastic processes; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386449

Filename

386449