Title :
Simulation and reduction of CMOS power dissipation at logic level
Author :
Dresig, F. ; Lanchés, Ph ; Rettig, O. ; Baitinger, U.G.
Author_Institution :
Tech. Univ. of Chemnitz, Germany
Abstract :
A logic simulation approach suitable to get information about the dissipated power of a system without the need of a specific current simulation is described. With this approach it is possible to retrieve estimations for average power dissipation under typical operating conditions. Furthermore a mapping approach which performs a power-minimal mapping for a given CMOS combinational circuit structure is suggested
Keywords :
CMOS logic circuits; circuit analysis computing; combinational circuits; logic CAD; CMOS power dissipation; average power dissipation; circuit structure; logic simulation approach; power-minimal mapping; Batteries; CMOS logic circuits; Capacitance; Circuit simulation; Combinational circuits; Frequency; Power dissipation; Power supplies; Switching circuits; Wiring;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386452
