A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensations

This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 V_pp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.