Title :
A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology
Author :
Koh, Jeongwook ; Lee, Jung-Eun ; Suh, Chun-Deok ; Kim, Hoon-Tae
Author_Institution :
Samsung Adv. Inst. of Technol., Samsung Electron. Co. Ltd., Kiehung
Abstract :
We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC´s.
Keywords :
1/f noise; CMOS analogue integrated circuits; CMOS digital integrated circuits; integrated circuit noise; operational amplifiers; 1/f-noise reduction architecture; CMOS Miller operational amplifier; continuous signal processing analog IC; digital CMOS technology; size 0.13 μm; time-continuous linear IC; voltage 1.5 V; Analog integrated circuits; CMOS technology; Circuit noise; Integrated circuit noise; Integrated circuit technology; Noise reduction; Operational amplifiers; Radio frequency; Semiconductor device noise; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357880
