Title :
Bit-alignment in hardware allocation for multiplexed DSP architectures
Author :
Schoofs, Koen ; Goossens, Gert ; De Man, Hugo
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
Finding a correct mapping of the bits of every signal onto the bit lines of a connection or operator terminal of multiplexed VLSI architectures is considered. An approach to solve alignment problems that occur in this mapping process is presented. Bit alignment is an essential element of the hardware allocation process for DSP applications. The result is a bit-true silicon compiler, which is able to implement every signal type exactly as specified in the behavioral description. This approach is exemplified with a case study
Keywords :
VLSI; circuit analysis computing; circuit layout CAD; digital signal processing chips; high level synthesis; architecture model; behavioral description; bit-alignment; bit-true silicon compiler; complex execution units; hardware allocation; high level synthesis; interconnectivity; multiplexed DSP architectures; multiplexed VLSI architectures; Application specific integrated circuits; Arithmetic; Digital signal processing; Hardware; High level synthesis; Multiplexing; Multiprocessor interconnection networks; Signal mapping; Silicon compiler; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386461
