A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System

Author

Kim, Hyejung ; Choi, Sungdae ; Yoo, Hoi-Jun

Author_Institution

KAIST, Daejeon

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

207

Lastpage

210

Abstract

A low power 16-bit RISC is proposed for body sensor network system. The proposed IPEEP scheme provides zero overhead for the wakeup operation. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16times16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 93.8%. The RISC is implemented by 1-poly 6-metal 0.18 um CMOS technology with 16 k gates. It operates at 4 MHz and consumes 24.2 uW at 0.6 V supply voltage.

Keywords

CMOS integrated circuits; biomedical equipment; data compression; low-power electronics; patient monitoring; personal area networks; reduced instruction set computing; telemedicine; wireless sensor networks; CMOS technology; IPEEP scheme; body sensor network system; energy consumption; lossless compression accelerator; low energy data compression; low power 16-bit RISC; size 0.18 mum; storage array; word length 16 bit; Base stations; Body sensor networks; CMOS technology; Compression algorithms; Data compression; Energy consumption; Reduced instruction set computing; Registers; Sensor systems; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357887

Filename

4197626