Title :
A 1.2V, 78dB HDSP ADC with 3.1V input signal range
Author :
Rajaee, O. ; Takeuchi, S. ; Aniya, M. ; Hamashita, K. ; Moon, U.
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A low power, high resolution two-step hybrid delta-sigma/pipelined modulator (HDSP) is presented. The feedback architecture of the HDSP modulator is modified to allow higher orders of noise shaping. The pipelined quantizer is simplified. Finally, the input signal range of the HDSP modulator is extended beyond the supply voltage. The prototype chip is implemented in a 0.18/im CMOS process. With a 1.56 MHz bandwidth, 2.6 mW analog power consumption and 1.2 V analog supply voltage, the measured dynamic range and SNDR of this prototype IC are 78 dB and 75 dB.
Keywords :
delta-sigma modulation; low-power electronics; pipeline arithmetic; quantisation (signal); HDSP ADC; bandwidth 1.56 MHz; delta-sigma/pipelined modulator; input signal range; noise shaping; pipelined quantizer; power 2.6 mW; size 0.18 mum; voltage 1.2 V; voltage 3.1 V; Bandwidth; Capacitors; Delay; Modulation; Noise; Noise shaping; Quantization;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716628
