Title :
Synthesis of weighted random sequences with application to testing of sequential circuits
Author :
Gloster, Clay, Jr. ; Brglez, Franc
Author_Institution :
ECE Dept., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The weights are stored and a weighted random sequence generator is used to produce the required test sequences during testing rather than storing the actual test sequence themselves. The generation of required weights is based on the dynamic scan algorithm, DYNASTEE. Experimental results demonstrate tradeoffs in test application time and in tester memory requirements, while maintaining 100% fault coverage of all target faults
Keywords :
application specific integrated circuits; built-in self test; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; ASIC; BIST; DYNASTEE; dynamic scan algorithm; fault coverage; test sequences; testing of sequential circuits; weighted random sequence generator; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Costs; Flip-flops; Heuristic algorithms; Random sequences; Sequential analysis; Sequential circuits;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386471
